In existing content processing System on Chip (“SoC”) designs, the incoming content packets are typically directly redirected to external memory storage prior to being processed. As illustrated in FIG. 1, an existing content processing SoC (“SoC 100”) may include two Packet Processing Controllers (“PPC 105” and “PPC 110”), a security accelerator (“SHA 115”), a central processing unit (“CPU 120”) and a memory control unit (“MCU 125”), all coupled via a Central Communications Bus 150 to external memory (“External Memory 130). Examples of PPCs include Gigabit Ethernet controllers, PCI Express graphics adapters and USB controllers.
In a typical content processing scheme today, encrypted packets may be received by PPC 105, stored in External Memory 130, read and processed from External Memory 130 by CPU 120, stored back in External Memory 130, then read and retransmitted by PPC 110. If the incoming packet includes encryption, PPC 105 may again store the packets in External Memory 130, SHA 115 may read and decrypt the packets then store them back in External Memory 130 prior to CPU 120 reading and processing the packets. Again, CPU 120 may store the processed packets back in External Memory 130 and the packets may then be read and retransmitted by PPC 110.
Transferring packets this way imposes significant performance bottlenecks on SoC 100. Each data store and fetch to External Memory 130 has a fixed latency that is typically governed by industry standards and cannot easily be changed. External Memory 130 may, for example, be double data rate (“DDR”) memory, governed by well-known DDR standards. As the number of PPCs in the system increases, the performance bottleneck becomes more pronounced.